110 lines
4.8 KiB
Plaintext
110 lines
4.8 KiB
Plaintext
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;; http://www.classiccmp.org/dunfield/r/8080.txt
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8080 instruction encoding:
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Conventions in instruction source:
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D = Destination register (8 bit)
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S = Source register (8 bit)
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RP = Register pair (16 bit)
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# = 8 or 16 bit immediate operand
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a = 16 bit Memory address
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p = 8 bit port address
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ccc = Conditional
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Conventions in instruction encoding:
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db = Data byte (8 bit)
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lb = Low byte of 16 bit value
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hb = High byte of 16 bit value
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pa = Port address (8 bit)
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Dest and Source reg fields:
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111=A (Accumulator)
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000=B
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001=C
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010=D
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011=E
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100=H
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101=L
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110=M (Memory reference through address in H:L)
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Register pair 'RP' fields:
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00=BC (B:C as 16 bit register)
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01=DE (D:E as 16 bit register)
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10=HL (H:L as 16 bit register)
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11=SP (Stack pointer, refers to PSW (FLAGS:A) for PUSH/POP)
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Condition code 'CCC' fields: (FLAGS: S Z x A x P x C)
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000=NZ ('Z'ero flag not set)
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001=Z ('Z'ero flag set)
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010=NC ('C'arry flag not set)
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011=C ('C'arry flag set)
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100=PO ('P'arity flag not set - ODD)
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101=PE ('P'arity flag set - EVEN)
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110=P ('S'ign flag not set - POSITIVE)
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111=M ('S'ign flag set - MINUS)
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Inst Encoding Flags Description
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----------------------------------------------------------------------
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MOV D,S 01DDDSSS - Move register to register
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MVI D,# 00DDD110 db - Move immediate to register
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LXI RP,# 00RP0001 lb hb - Load register pair immediate
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LDA a 00111010 lb hb - Load A from memory
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STA a 00110010 lb hb - Store A to memory
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LHLD a 00101010 lb hb - Load H:L from memory
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SHLD a 00100010 lb hb - Store H:L to memory
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LDAX RP 00RP1010 *1 - Load indirect through BC or DE
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STAX RP 00RP0010 *1 - Store indirect through BC or DE
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XCHG 11101011 - Exchange DE and HL content
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ADD S 10000SSS ZSPCA Add register to A
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ADI # 11000110 db ZSCPA Add immediate to A
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ADC S 10001SSS ZSCPA Add register to A with carry
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ACI # 11001110 db ZSCPA Add immediate to A with carry
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SUB S 10010SSS ZSCPA Subtract register from A
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SUI # 11010110 db ZSCPA Subtract immediate from A
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SBB S 10011SSS ZSCPA Subtract register from A with borrow
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SBI # 11011110 db ZSCPA Subtract immediate from A with borrow
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INR D 00DDD100 ZSPA Increment register
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DCR D 00DDD101 ZSPA Decrement register
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INX RP 00RP0011 - Increment register pair
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DCX RP 00RP1011 - Decrement register pair
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DAD RP 00RP1001 C Add register pair to HL (16 bit add)
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DAA 00100111 ZSPCA Decimal Adjust accumulator
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ANA S 10100SSS ZSCPA AND register with A
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ANI # 11100110 db ZSPCA AND immediate with A
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ORA S 10110SSS ZSPCA OR register with A
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ORI # 11110110 ZSPCA OR immediate with A
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XRA S 10101SSS ZSPCA ExclusiveOR register with A
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XRI # 11101110 db ZSPCA ExclusiveOR immediate with A
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CMP S 10111SSS ZSPCA Compare register with A
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CPI # 11111110 ZSPCA Compare immediate with A
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RLC 00000111 C Rotate A left
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RRC 00001111 C Rotate A right
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RAL 00010111 C Rotate A left through carry
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RAR 00011111 C Rotate A right through carry
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CMA 00101111 - Compliment A
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CMC 00111111 C Compliment Carry flag
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STC 00110111 C Set Carry flag
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JMP a 11000011 lb hb - Unconditional jump
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Jccc a 11CCC010 lb hb - Conditional jump
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CALL a 11001101 lb hb - Unconditional subroutine call
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Cccc a 11CCC100 lb hb - Conditional subroutine call
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RET 11001001 - Unconditional return from subroutine
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Rccc 11CCC000 - Conditional return from subroutine
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RST n 11NNN111 - Restart (Call n*8)
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PCHL 11101001 - Jump to address in H:L
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PUSH RP 11RP0101 *2 - Push register pair on the stack
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POP RP 11RP0001 *2 *2 Pop register pair from the stack
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XTHL 11100011 - Swap H:L with top word on stack
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SPHL 11111001 - Set SP to content of H:L
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IN p 11011011 pa - Read input port into A
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OUT p 11010011 pa - Write A to output port
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EI 11111011 - Enable interrupts
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DI 11110011 - Disable interrupts
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HLT 01110110 - Halt processor
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NOP 00000000 - No operation
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*1 = Only RP=00(BC) and 01(DE) are allowed for LDAX/STAX
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*2 = RP=11 refers to PSW for PUSH/POP (cannot push/pop SP).
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When PSW is POP'd, ALL flags are affected.
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