From 43ba3c82522c4ddf497e45fdd16b75c0d9c0574a Mon Sep 17 00:00:00 2001 From: Yonggang Wang Date: Fri, 6 Mar 2020 13:58:34 +0800 Subject: [PATCH] panel design file ready --- design/panel.svg | 416 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 416 insertions(+) create mode 100644 design/panel.svg diff --git a/design/panel.svg b/design/panel.svg new file mode 100644 index 0000000..c4903a8 --- /dev/null +++ b/design/panel.svg @@ -0,0 +1,416 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + INTE + + + PROT + + + MEMR + + + INP + + + MI + + + OUT + + + HLTA + + + STACK + + + WO + + + INT + + + D7 + + + D6 + + + D5 + + + D4 + + + D3 + + + D2 + + + D1 + + + D0 + + + A7 + + + A6 + + + A5 + + + A4 + + + A3 + + + A2 + + + A1 + + + A0 + + + A15 + + + HLDA + + + A14 + + + A13 + + + A12 + + + A11 + + + A10 + + + A9 + + + A8 + + + WAIT + + + SENSE SW. + + + Address + + + Data + + + STOP + + + RUN + + + EXAMINE + + + EXAMINE + NEXT + + + SINGLE + STEP + + + DEPOSIT + + + DEPOSIT + NEXT + + + RESET + + + CLR + + + PROTECT + + + AUX + + + UNPROTECT + + + AUX + + + 7 + + + 6 + + + 5 + + + 4 + + + 3 + + + 2 + + + 1 + + + 0 + + + 15 + + + 14 + + + 13 + + + 12 + + + 11 + + + 10 + + + 9 + + + 8 + + + STATUS + + + OFF + + + ON + + + + + + + +